The Fetch part of the cycle, and each Opcode operation consist of a number of Microcodes, stored in the CU PROMS, each of 16 bits. Via the control lines, these Microcodes control the registers, Main Memory and the Clock. The output of the CC is attached to the address lines of the 2 CU PROMS in parallel. At each clock pulse the CC counts up 1, so addressing the next memory location in the CU PROMS and thus putting the next microcode onto the 16 control lines. Two control lines feed back from the CU PROMS to the CC: one of these sets the CC back to 0 for the start of each Fetch operation, the other loads in the Opcode to begin the Execute part of the cycle. In other words a jump is made to a new CU PROM address (the same as the Opcode), which holds the first Microcode of that Opcode operation.

Table1 below shows all the Microcodes which constitute both the Fetch operation and the set of 7 Minimum Opcodes.

Table1.xls

Each instruction is made up of 2 bytes, the first being the Operand (Data) and the second byte being the Opcode. During the Fetch part of the cycle the first of the pair of bytes ( the Operand) is transferred to the IR, while the second byte (Opcode) goes straight into the CC. The PC is incremented by 1 twice during the Fetch operation.

Some control lines are “active low”, that is they are normally 1 ( 5volts) and when set to 0 (0volts) activate the device they are controlling. Table1 shows the Action & Rest states for each control line. For the Up (+1) & Down (-1) actions the transition from L0 (0) to HI (1) triggers the action; because the Rest state is 1 these lines have to go to 0 in the previous Microcode to the one which “fires” them. Table1 shows in green the control line conditions which are Not rest state and in yellow those where there is a return to Rest state.

Fetch operation in detail

Microcode 0 :
CU pin C active , puts PC contents on the bus
CU pin 8 active , bus contents go into AR
CU pin B goes LO, ready to go HI next time to up the PC (+1)

Microcode 1 :
CU pin C goes back to rest, PC disconnects from bus
CU pin 8 goes back to rest, AR not receiving from the bus
CU pin B goes HI, PC increments (+1)
CU pin 9 active , read from MM, contents put on bus
CU pin F active , bus contents go into IR

Microcode 2 :
CU pin 9 goes back to rest, MM disconnects from bus
CU pin F goes back to rest, IR not receiving from the bus
CU pin C active , puts PC contents on the bus
CU pin 8 active , bus contents go into AR
CU pin B goes LO, ready to go HI next time to up the PC (+1)

Microcode 3 :
CU pin C goes back to rest, PC disconnects from bus
CU pin 8 goes back to rest, AR not receiving from the bus
CU pin B goes HI, PC increments (+1)
CU pin 9 active , read from MM, contents put on bus

Microcode 4 :
CU pin 9 active , read from MM, contents still on bus
CU pin 6 active , bus contents go into CC

Let’s take the case where we are at the very start of a program, so PC will be at 0 initially, and let’s have 18H & 10H as the first 2 bytes in the program, at MM addresses 0 & 1. So what will have happened is this:

Microcode 0, PC = 0, goes into AR
Microcode 1, Contents of MM address 0 (18H) go into IR ( this is the Operand), PC goes up 1 to 1
Microcode 2, PC = 1, goes into AR
Microcode 3, PC goes up 1 to 2 (ready for the next Fetch cycle)
Microcode 4, Contents of MM address 1 (10H) go into CC ( this is the Opcode)

So the CC now jumps to Microcode 10H, which is the first Microcode in the LDA instruction

Execute Instruction LDA ( Opcode 10H) in detail

Microcode 10 :
CU pin 9 active , read from MM, contents still on bus

Microcode 11 :
CU pin 9 goes back to rest, MM disconnects from bus
CU pin E active , puts IR contents on the bus
CU pin 8 active , bus contents go into AR

Microcode 12:
CU pin E goes back to rest, IR disconnects from bus
CU pin 8 goes back to rest, AR not receiving from the bus

Microcode 13:
CU pin 9 active , read from MM, contents put on bus
CU pin 1 active , bus contents go into AL

Microcode 14:
CU pin 9 active , read from MM, contents still on bus
CU pin 1 goes back to rest, AL not receiving from the bus
CU pin 5 active , CC resets to 0 ( to start the next Fetch)

Continuing with our example program, with 18H already in the IR from the Fetch. What’s happened is:

Microcode 10, Nothing, (Glitch avoider)
Microcode 11, IR contents (18H) (this is the Operand) go into AR
Microcode 12, Nothing, (Glitch avoider)
Microcode 13, Contents of MM at address 18H go into AL
Microcode 14, CC reset to 0

So the CC now jumps to Microcode 0, which is the first Microcode in the Fetch operation

So what we’ve done in this first Fetch/Execute cycle is transfer the contents of the MM address specified by the Operand (1st byte ( no 0) in the program) to the AL. We’ve also incremented the PC from its initial 0 value to 2 and also got back to Microcode 0 ready to do the next Fetch. Let’s continue the program example with 1A and 20 as the next pair of bytes in the program, at addresses 2 and 3.

2nd Fetch operation
Identical in structure to the first one, but at the end of it we have:
The new Operand (1A) in the IR
PC incremented to 4 ready for the 3rd Fetch
CC has jumped to Microcode 20H, which is the first Microcode in the STO instruction (Opcode 20H)

Execute Instruction STO ( Opcode 20H) in detail

Microcode 20:
CU pin 9 active , read from MM, contents still on bus

Microcode 21:
CU pin 9 goes back to rest, MM disconnects from bus
CU pin E active , puts IR contents on the bus
CU pin 8 active , bus contents go into AR

Microcode 22:
CU pin E goes back to rest, IR disconnects from bus
CU pin 8 goes back to rest, AR not receiving from the bus
CU pin 0 active , AL contents put on bus
CU pin A active , write to MM from bus

Microcode 23:
CU pin 0 goes back to rest, AL disconnects from bus
CU pin A goes back to rest, MM not writing
CU pin 5 active , CC resets to 0 ( to start the next Fetch)

Continuing with our example program, with 1A already in the IR from the Fetch. What’s happened is:

Microcode 20, Nothing, (Glitch avoider)
Microcode 21, IR contents (1A) ( this is the Operand) go into AR
Microcode 23, Contents of AL go into MM at address 1A
Microcode 24, CC reset to 0

So what we’ve done in the 2nd Fetch/Execute cycle is transfer the contents of AL into the MM address specified by the Operand (3rd byte (no 2 ) in the program) We’ve also incremented the PC from its initial 2 value to 4 and also got back to Microcode 0 ready to do the next Fetch.

Last edited Dec 15, 2008 at 9:40 AM by dmgant, version 6

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