This project is read-only.
The LDA & STO Instructions have already been explained in the [Fetch/Execute implementation] section of this project.

Table1 below shows all the Microcodes for the 7 Instructions (Opcodes).


The INC & DEC Instructions

These have Opcodes 30H & 40H, and if you’ve followed us so far in the [Fetch/Execute implementation] section then using the Microcode table they’re pretty self explanatory. In Microcodes 31 & 41 respectively they use control lines 4 and 3 respectively to up (+1) & dn (-1) the AL

The JMP & JMZ Instructions

These have Opcodes 50H (unconditional jump) & 60H (conditional jump). Table1 shows that in Microcode 51 the IR contents are transferred to the PC. As usual the IR holds the Operand, which is the address in the program we want to jump to. So as this is now in the PC, on the next Fetch operation we get the next byte from MM from the jump address.
Microcode 61 in the JMZ (conditional jump) is similar, except that control line 2 is active, rather than line D in Microcode 51. Line D directly loads the PC from the bus, but line 2 (the check (ch) line) only loads the PC from the bus If the AL contents are 0. This is achieved using an AND gate, & an 8 input NOR gate which is connected to the 8 bits held in the AL

The HLT Instructions

This has Opcode 70H, and using Table1 you can see that in Microcode 71 the contents of the AL are put on the bus. Microcode 72 activates control line 7 which stops (st) the Clock (CL)

The attached Program1shows an example of a complete program which begins with the 4 bytes in the example we’ve been working through in the fetch/execute discussion. It uses addresses 18, 19 and 1A to store data. In action, the MISCE hardware demonstrates every microcode as it runs through a program either one step at a time or at speed, showing on its LEDs the contents of each register, what’s on the bus, and the state of the control lines.


Last edited Dec 15, 2008 at 11:18 AM by dmgant, version 6


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